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ADP1043A
CURRENT SHARING (SHARE)
The ADP1043A supports both analog current sharing and
digital current sharing. It is recommended that analog current
sharing be used because it offers improved performance over
digital current sharing. Digital current sharing requires a load
line of >15 mΩ to prevent oscillation between units. The analog
current sharing scheme has no such issues.
Using Register 0x29, Bit 3, it is possible to program the
ADP1043A to use the CS1 current information or the CS2
current information for current sharing.
Analog Current Sharing
The ADP1043A supports analog current sharing. The current
The power supply with the highest current controls the bus
(master). A power supply that is putting out less current (slave)
sees that another supply is providing more power to the load
than it is. During the next cycle, the slave increases its current
output contribution by increasing its output voltage. This cycle
continues until the slave outputs the same current as the master,
within a programmable tolerance range. Figure 22 shows the
configuration of the digital share bus.
V DD
SHAREi
reading from CS1 or CS2 can be output to the SHAREo pin in
CURRENT SENSE
INFO
DIGITAL
SHAREo
the form of a digital bit stream, which is the output of the current
sense ADC (see Figure 23). The bit stream is proportional to the
current being delivered by this unit to the load. By filtering this
digital bit stream using an external RC filter, the current informa-
tion is turned into an analog voltage. This means that there is
now an analog voltage that is proportional to the current being
POWER SUPPLY A
WORD
SHAREi
SHARE
BUS
delivered by this unit to the load. This voltage can be compared
to the share bus. If the unit is not supplying enough current, an
CURRENT SENSE
INFO
DIGITAL
WORD
SHAREo
error signal can be applied to the VS3 feedback point. This signal
causes the unit to increase its output voltage and, therefore, its
current contribution to the load.
For more information about the analog current share function-
ality, including schematics and measurements in different fault
and setup conditions, see the product page for the ADP1043A.
Digital Share Bus
The digital share bus scheme is similar in principle to the tradi-
tional analog share bus scheme. The difference is that instead of
using a voltage on the share bus to represent current, a digital
word is used.
The ADP1043A outputs a digital word onto the share bus. The
digital word is a function of the current that the power supply is
providing (the higher the current, the larger the digital word).
CURRENT
POWER SUPPLY B
Figure 22. Digital Current Share Configuration
The digital share bus is based on a single-wire communication
bus principle; that is, the clock and data signals are contained
together.
When two or more ADP1043A devices are connected, they
synchronize their share bus timing. This synchronization is
performed by the start bit at the beginning of a communications
frame. If a new ADP1043A is hot-swapped onto an existing
digital share bus, it waits to begin sharing until the next frame.
The new ADP1043A monitors the share bus until it sees a stop
bit, which designates the end of a share frame. It then performs
synchronization with the other ADP1043A devices during the
CS2+
CS2–
VOLTAGE
CURRENT
SENSE
ADC
BIT STREAM
SHARE
BUS
SHAREo
BIT STREAM
LPF
Figure 23. Analog Current Share Configuration
2 STOP BITS
(IDLE)
PREVIOUS
FRAME
START BIT
0
8-BIT DATA
FRAME
2 STOP BITS
(IDLE)
START BIT
0
NEXT FRAME
Figure 24. Digital Current Share Frame Timing Diagram
Rev. 0 | Page 20 of 72
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